1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, particularly, to a semiconductor device having a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) and a method of manufacturing the same.
2. Description of the Related Art
A power device such as a power MOSFET normally uses a vertical MOSFET. The power MOSFET typically has a trench gate structure where a gate electrode is formed inside a trench. FIG. 6 is a sectional view showing the structure of a conventional power MOSFET. In the MOSFET of FIG. 6, an epitaxial layer 2 is formed all over the surface of a semiconductor substrate 1. A base region 3 and a source region 4 are successively formed on the epitaxial layer 2. A trench 5 penetrates through the source region 4 and the base region 3. A gate oxide film 6 is formed on the inner surface of the trench 5. A gate electrode 7 is formed by depositing polysilicon all over the surface of the semiconductor substrate 1 and etching it back. The polysilicon different from the gate electrode 7 that is deposited inside the trench 5 by the etch-back is then etched away.
In a conventional semiconductor device, an interlayer insulation film 8 is deposited all over the surface of the semiconductor substrate 1. After that, the interlayer insulation film 8 is selectively etched to create contact holes 9 that reach the base region 3 and the gate electrode 7. Then, a conductive plug 10 is formed to fill each contact hole 9. After that, a wiring layer 11 is deposited on the interlayer insulation film 8 and patterned into a source line and a gate line.
The conventional MOSFET forms the source region 4 all over the base region 3 and etches the silicon to the base region 3 when creating the contact hole 9. However, etching the silicon to the base region 3 results in etching the polysilicon of the gate electrode 7 also (see FIG. 6).
A technique that forms the source region on the base region and creates the contact hole that penetrates through the source region is described in Japanese Patent Translation Publication No. 2003-515915.
The polysilicon used for the gate electrode 7 contains a high concentration of impurities in order to reduce resistance and therefore an etching rate is higher than the source region (cf. Japanese Unexamined Patent Publication No. 2000-183343).
The present invention has recognized that the conventional MOSFET has a problem that the gate electrode 7 is etched rapidly and therefore it is etched to the bottom to cause a short-circuit between the gate and drain.